DVCon 2006 World Peace with attitude ...
February 26, 2006 Editor's Note: DVCon 2006 took place on February 22nd, 23rd, and 24th. Conference Chair Karen Bartleson from Synopsys and Program Chair Steve Bailey from Mentor hosted a Press Luncheon on the 22nd. At that event, they were very happy to report that this year's conference was shaping up to be the most highly attended DVCon ever. They also said the morphing of the conference from earlier versions highlighting VHDL or Verilog, the subsequent version of the conference, HDLCon, and the current version, DVCon, have all had an important impact on the underlying efforts to pursue language standards across the industry. Culinary Note: Next year's DVCon 2007 Chair will be Gabe Moretti. Not surprisingly, this year's Press Lunch menu showcased some fabulous salmon. Moretti's Press Lunch next year will have to work hard to live up to this year's standard. Undoubtedly he'll rise to the challenge. **********************************************************February 15, 2006 DVCon is a small conference and it's happening next week. It's a conference that's focused, accessible, and at the core of your world if you work in an HDL or a verification language, or have any interest whatsoever in the world of hardware design and verification. DVCon is also in Silicon Valley. The epicenter of the design tools world is in Silicon Valley. Yes, I know that many people would argue that there are multiple foci that define the design tools world today, and I would be among those who have argued it is so. Nonetheless, there is something about Silicon Valley, it's environs and mindset that continues to speak directly to the heart of the design tools world. The design tools world is about innovation – not just any kind of innovation, but a focused and intimate kind of innovation that happens way down at the level of the code, way down at the implementation of the design on the silicon – and these days, way down at the level of the materials themselves. And this kind of intimate innovation happens one on one, with people talking and arguing and competing in a small microcosm of a world where they can support each other and then yell at each other and then enjoy a great meal and a glass of wine together – all in the same day. Of course, DVCon is not about the materials, substrates, dopants, junctions, or etch. DVCon is smack dab between the physics of the thing and the high level architecting of the thing. It's about using the languages and the tools, conceiving of the design, and verifying that the design you developed has been sufficiently evaluated to let it fly out to the fab, onto the market, and into the hands of the most critical and fickle community on earth – consumers. So, do you belong at DVCon? If you're reading this, you most certainly do. Last year there were a few shy of 600 folks who came, and this year the conference organizers expect even more. Of last year's attendees, 60 percent said they were interested in verification and 40 percent said their main focus was design. But that's way too simple a way to slice the pie. Several weeks ago, I had a chance to speak to two of the people who are conducting the show this year – Conference Chair Karen Bartleson from Synopsys and Program Chair Steve Bailey from Mentor Graphics. In talking to these people, you pick up a nuance of what the conference is about. DVCon is about conversation and it's about compromise. Those two sentiments rule the day at DVCon. Steve Bailey told me, "Verification issues really pique people's interests. So our program this year is larger than it's been in several years – we've even added a third track. There used to be two tracks, one for design and one for verification. But we're seeing more verification papers than design papers, so now we try not to force the topics into one track or the other. Also, now there's a third track that includes formal verification discussions." "[Meanwhile], we're also seeing an increased interest in higher levels of abstraction – SystemC and transaction level modeling. SystemC has been a popular topic for some time, and we don't see that changing." [The North American SystemC User's Group is having a meeting in conjunction with DVCon on February 22nd.]Steve also told me, "In addition to the three tracks, we also have three embedded tutorials on Friday afternoon – one that will discuss what SPIRIT is doing in the area of XML, one will cover the SystemVerilong Direct Programming Interface, and one will cover VHDL's fixed and floating point types. There are also four tutorials related to verification methodologies sponsored by Mentor, Synopsys, Cadence and ARM. And, we also have a special session on overall good design practices." "The EDA companies plan for DVCon like they plan for DAC – they know they may not have a release quite ready when they submit a paper proposal several months before, but by the time they get to DVCon, the release may be coming up shortly and then they can talk about the key capabilities. This year we had approximately 100 paper submissions and 30 were selected." I asked Steve if DVCon can be taken on the road, even though I feel it to be firmly tied to Silicon Valley. He said, "Accellera does two to three events a year in Japan, [so we know there's interest], but there's a big difference between putting on a full conference and getting people together for a half day of conversation. So, we need to work on that. Also, there's talk of getting the conference over to Europe as well. Right now, we get people from all three regions attending the conference in Silicon Valley, but the largest number of attendees still reside in the immediate area." Karen Bartleson told me, "One of the things we did with Accellera was to combine the VHDL user meeting on the East Coast with the Verilog meeting on the West Coast to create HDLCon, and then DVCon. What's really interesting is that HDLCon was based on language standards and language-based design. But combining design and verification raised it up a level to say that there's more than just languages – now it's about finding out how to benefit design by combining the languages." "Similarly, DVCon is not just about design or verification – it's about combining those [processes]. The reality of that emphasis became clear with the emergence of SystemVerilog. Of course, we don't want to reduce the focus on design at the conference, but as Steve said – it just doesn't make sense any more to think of design and verification as separate entities." Karen also told me, "Our keynote is going to be different this year. John Chilton – yes, he's from Synopsys – will not just be talking about emerging technologies. He going to talk about the costs of doing design and the surprises you might come across when you do a design these days. I think his talk will be a breath of fresh air, because it won't be just focused on a language standard. It will have a broader perspective." Steve said the broader perspective is important: "Typically we have been focusing on the design and the verification side of the business because that's what been of interest to the EDA vendors. But now we see that the senior guys in IP are coming to the conference as well. It's a recognition in the industry that if a technology helps the end user and broadens the market, it may belong at DVCon." Karen said, "I was talking to Dennis Brophy [Accellera] the other day, and we were talking about how cooperation helps the design community. That's definitely what you will see this year at DVCon." So why is cooperation and compromise the over-arching sentiment for the design and verification guys who hang out together at DVCon? Because, up until this moment – and by the looks of things for quite some time to come – hardware design has been about using a plethora of different tools from a range of different vendors that function on a variety of different platforms and dumping the results into a patchwork of different databases. I know, I know that's all changing – and changing fast. But, why is it changing? It's changing because people like Dennis Brophy and Shrenik Mehta and Gabe Moretti and Victor Berman and Vassilios Gerousis and Steve Schulz and Rich Goldman and Karen Bartleson and Johny Srouji and Rich Faris and Harry Foster and others who haven't been named here, but should have been, have worked together for years now to try to defeat the territorialism, proprietary-ism (is that a word?), and plain-long selfishness that were the watch words in EDA. Compromise and patience have now broken those ice flows apart, and designers today are reaping the benefits by way of the standards and language specifications hammered out by dogged consensus-builders who felt the industry could do better and proved it. Karen told me, "The collegiality you're seeing in the industry is a sign that EDA is maturing. I've been involved in standards for 10 years, and although there are still a few pockets of nonsense going on here and there, in general I've seen a real maturing in the whole process." Of course, lest we wax too poetic about the maturity and wisdom in the industry – or the folks attending DVCon – let's also remember that the conference is not just about peacemakers, consensus builders, and standards warriors. DVCon also showcases a different kind of dynamic as well. Somewhere in the late afternoon hours of the middle day of the conference, ESNUG's John Cooley assembles a high-profile panel of decision makers who for some reason are willing to sit up in front of a crowded room and take thorny questions from John about a range of topics they probably would rather not address in public. Questions about unremarkable corporate accomplishments or technologies that have failed to live up to their potential. In Cooley's hour, DVCon becomes an intimate community full of prickly people who all consider themselves pals, because they're united in knowing that John will be just rude enough to keep it interesting and just impatient enough to keep it moving. Steve Baily told me, "I always attend the Cooley panel because, although personally I don't like the discussions about lawsuits that sometimes go on there, when the panel is on – especially when the discussion is on design and verification – it's always fun to see what will come up. Cooley determines the content of the panel discussion in a survey that he puts out close to the actual event, so it's cloaked in secrecy. No matter what comes up on the panel, you always get some information that's interesting." I asked Karen if she was ever concerned that DVCon's advocacy for World Peace, paticularly between language factions, gets a little muddled when Cooley's panel is thrown into the mix. She said, "I don't think the Cooley panel detracts from the collegiality of DVCon or the industry. DVCon is about sharing ideas and coming up to speed on the latest in the languages and technologies – and even with Cooley's panel thrown into the mix, DVCon is still about World Peace." Then Karen laughed and said, "I like to think of it as World Peace with attitude!" ************************************** DVCon is happening February 22nd to the 24th at the DoubleTree Hotel in San Jose. **************************************
Peggy Aycinena owns and operates EDA Confidential. She can be reached at peggy@aycinena.com
|