2) The concomitant trend to "one-time sales of technology" in the context of alliances and consortia.

(1) Some entrants are trying to develop better, faster RET tools. This is quite understandable given the importance of RET, but it’s a fairly mature market controlled by two dominant suppliers.

(2) Lithography simulation is another active area. The underlying technologies have been around for a while, but there are some new entrants in that market, simulators are being bolted into layout tools, etc.

(3) Quite a few companies are adding DFM awareness to physical design tools such as routers and layout editors. This is an interesting segment: certainly, one defensible tenet is that much of DFM should reside in the detailed router.

(4) Critical area analysis (CAA) tools that address chip failures due to random defects are a very old technology. In fact, I remember inviting survey talks on this subject from Professor Maly of CMU and Professor Koren of U. Mass. Amherst when I organized a "DFM" special session at the 1996 Physical Design Workshop. Today, the CAA tools are new to the commercial market, with several vendors at play. This is part of the phenomenon of outsourcing from IDMs that I mentioned earlier.

(5) CMP simulation is another "old" technology that is being outsourced from the IDMs.

(6) Many companies are further commoditizing technologies that are used in process bring-up and yield ramping – process characterization vehicles, scribe-line structures, etc. This is another technology that is well understood by the IDMs. The fact that this is perceived as a market gives some insight into today’s fabless-foundry dynamic.

(7) Statistical extraction and analysis tools are being pursued by several companies. As I mentioned earlier, in my view this isn’t the low-hanging fruit. We should first model/predict/compensate for the systematic variations, and minimize the design’s sensitivity to variation sources, before embarking on SSTA.

(8) One new type of DFM tool emerging today uses the design’s power and timing requirements to drive the manufacturing process. This type of solution can also bring manufacturing awareness upstream into the design process. The net result is fewer "parametric" failures.

First trend – The failure of WYSIWYG at 90-nanometers and below has motivated tools for shape and thickness simulation. But, we’re still seeing an emphasis on geometric criteria (through process window hot-spots, etc.) over electrical criteria (leakage, timing variation, etc.), on library and IP-development use models over full-chip use models; and on analyses over optimizations.

Second trend – "Uncontrollable variation" has motivated experiments with statistical analysis.

Third trend – Established internal technologies are being taken out of IDMs and commoditized. Two prominent examples are defect-oriented yield analysis such as critical area, pattern hotspot finding, and post-route layout optimizations such as via/contact doubling, "PDFx" layout variant methodologies, and wire spreading, etc.

Q – With respect to the physics, at what process node do quantum tunneling and probabilistic atomic behavior become overriding physical concerns?

Kahng – Hmmm. I will take the easy out, and latch onto your word "overriding." The easy answer – almost by definition – is that these effects can never become overriding concerns, because then the semiconductor roadmap would be dead in the water.

For example, we do see band-to-band tunneling as a factor in leakage current and Iddq testability as we go to 65 nanometers and beyond. But at some point, alternative device architectures would be used as needed.

With respect to probabilistic atomic behavior, one source of randomness is especially important with respect to power – random dopant fluctuations [RDF]. This is the "probabilistic atomic effect" that the ITRS Design Chapter has always mentioned as a long-term challenge, since the late 1990s.

In fact, I recently discussed this with Professor Dennis Sylvester at University of Michigan, as the topic came up in another context. To basically paraphrase Dennis, RDF will be problematic for ultra-low voltage designs in 65, 45, and 32 nanometers, but will likely be suppressed by undoped channels in double-gate FETs beyond this point.

Even in these technology nodes, the impact of RDF is lessened due to the fact that its largest impact is on power, but power is more aided by the central limit theorem than timing. Also, for example, the shift away from super-pipelining will allow for more averaging of delay across gates in a path.

The point is that process integration, device architecture, and even chip micro-architecture will all be brought to bear in time to prevent RDF from becoming an "overriding physical concern."

Kahng – Theoretically, there is always hope.

We can usually gain accuracy at the cost of throughput. We can make scanner-specific or reticle position-specific place-and-route and OPC solutions, at the cost of manufacturing flexibility. We can return to gate array-like templates, at the cost of designer freedom. The constraint is that "cost" must be consistent with sufficient ROI.

So, in a practical sense, I think there is very little hope. Indeed, going back to your earlier question, DFM must be the technology the buffers and works around all of these "red bricks" in the process technology roadmap.

Kahng – I personally distinguish the terms based on their connotations of impact.

To me, DFY connotes "incremental enhancement of yield" – perhaps 2 percent, or 3 percent, maybe 5 percent more sellable die per wafer – or else a modest acceleration of the yield learning process. Examples would include several of those first-wave "DFM simulators" I spoke of earlier.

On the other hand, DFM to me means a substantial boost – an enabling "big win."

To have "legs" in my view, a DFM technology must a) solve a "heart attack" – tapeout versus no tapeout, production versus no production; b) be difficult to develop – for example, an optimization technology; (c) be used by the designer as high up in the flow as possible; and (d) add value to the process just as a new manufacturing tool would – in other words, it enables a manufacturing solution.

Perhaps, in five years we will be able to clearly distinguish a set of OPC/RET technologies, a set of DFY technologies and, I hope, a set of true DFM technologies that satisfy the above criteria.

Kahng – DFT is one of the last big open frontiers for DFM, with DFV – design for value – being another. DFT and ATE tools together offer tremendous opportunities not only for yield diagnosis and learning, but also for new paradigms of adaptivity in the manufactured IC. DFT is definitely one of the technology areas I wish I understood better.

Kahng – "All of the above," plus test equipment makers, yield management and metrology system providers, and even the "green / clean-tech" segment of the semiconductor ecosystem.

Design technology is already understood to include the mask flow – OPC, mask data prep, etc. As design technology takes on the burden of "equivalent scaling" to maintain the Moore’s Law trajectory, equipment vendors must closely match their tool capabilities to what EDA can help work around. An early example of this was the X Initiative’s octilinear routing and its enablement across EDA, mask, and equipment sectors.

As an industry, we need to build the bridges that allow designers to work around the "red brick" challenges of uncontrollable variation, unavoidable leakage that comes from scaling device speeds and thinner gate oxides, and so on. One common motif shared by these bridges is comprehension of systematic variation in the manufacturing process. In other words, wherever we can model, predict and compensate for systematic variations, we can achieve smaller guardbands and more robust, variation-tolerant designs.

Chip design – up through floorplanning and synthesis/place-and-route – is capable of leveraging knowledge of many manufacturing parameters including crystal orientation of the wafer, fracturing of post-OPC shapes and location of major field boundaries in the mask write, x-versus-y asymmetry and lens aberration maps in the step-and-scan tool, and wafer-scale radial biases of etch and CMP.

There are lots of possibilities here, all with concrete value. My group’s research is aimed at creating and exploiting such bridges, so that some day "all of the above" will properly connect.

Kahng – Yes, designers are very smart, but even a "21st-century IC designer" cannot be infinitely broad and deep. I place a lot of value on the use of methodology to orthogonalize concerns, and ultimately to give designers the freedom from choice.

Just as Aart said, the designer ends up not having to think about low-value or well-understood things. But, in my view, this is not necessarily because EDA tools can "think." Rather, it is because the tools embody a methodology that restricts choice, and therefore remove the need to think.

Kahng – I have great respect for Raul, Antun Domic, Aart, Chi-Foon Chan, and many others at Synopsys. Indeed, all across the EDA industry there is so much energy and hard work.

I saw Raul’s keynote at ISQED 2006 a few weeks ago, and was extremely impressed. Synopsys certainly has made strategic acquisitions (ISE, HPL) and has strong building blocks. At the same time, perhaps Raul and I have different definitions of "a complete DFM solution."

Recall that a DFM flow must drive design intent into manufacturing, bring systematic variation awareness into design, and do this without changing the flow.

Recall that DFM is distinct from OPC/RET, and distinct from DFY. It must solve a "heart attack," embody difficult optimization technology, be used by the designer, and yet be enabling to the manufacturing solution.

Recall that a complete DFM solution will need to go far beyond "whatever IBM has been making for the past decade," and that we really need to question straight-line thinking that takes us to statistical timers, and the embedding of litho simulators into layout tools.

Whether it’s the router, or connections to the mask flow, or parametric yield optimization, or next-generation modeling standards, or wafer-level variability awareness, or stress/strain awareness in layout – there are still too many open problems and technologies yet to be developed. So, with all respect to Raul, I don’t think that any one company yet has a complete DFM solution.

Kahng – Actually, optical lithography and CMOS will take us pretty far. We should be down in the 22-nanometer or 16-nanometer node before running into fundamental roadblocks that have not already been solved by novel device architectures, new nonvolatile memory technologies, and multi-technology integration – die stacking or multiple device layers.

Self-assembly is an interesting idea, but perhaps also keep an eye on "directed assembly" – for example, the great work being done by Charles Lieber’s group at Harvard.

I don’t see that the "beyond-CMOS" technologies – carbon nanotubes, silicon nanowires, and DNA, etc. – are going to serve as replacements for CMOS, in the immediate future or perhaps ever. Rather, these are complements to silicon as we know it today.

Kahng – I think Chenming is absolutely right. There will always be a place for CMOS and for silicon as the basis for circuit integration. We have been riding the process technology wave for so long that we’ve left orders of magnitude on the table with respect to computational and signaling efficiencies.

We haven’t yet made any significant efforts with respect to the third dimension of integration. Architecturally, we’re still largely synchronous. At the same time, technologists can already see how to take existing flash and logic down to below 30 nanometers.

So, it’s not that it is "impossible" to move beyond our current infrastructure – rather, it is unnecessary to do so – not to mention extremely expensive!

Kahng – The ITRS roadmap projects the continued use of lithography to manufacture CMOS through the 14-nanometer node in year 2020. And, perhaps, we will find that the roadmap "stretches" a bit, in a principled and planned way, as we work through 45-nanometer and 32-nanometer transitions.

And as I just mentioned, we will also keep on using CMOS long after the "end of the roadmap" – just as plenty of manufactured silicon today is 0.5-micron CMOS, even though we’re prototyping 45-nanometer products today. There will be plenty of time for DFM companies to develop useful products that extend the life of CMOS even further.

Kahng – In your previous column that describes Samie Samaan’s comments on parameter variations, you mention how Intel comprehends die-to-die, within-die, random, systematic, etc. variations, and can even design around such variations. This is the whole point of being an IDM – to be able to co-optimize the product and the process and maximally extract value from fab technology.

But Intel is unique in its product focus, its capex, its value per wafer, etc. Fewer and fewer IDMs can hope to do this. As the IDMs increasingly go fabless or fab-light, their ability to maintain and extend unique and differentiated DFM solutions will decrease. This creates a vacuum that will be filled by niche, as well as broad-line tool providers in the DFM market.

Of course, at the same time, economies of scale and the market dynamics of the semiconductor supplier industries are causing consolidation to just a few "super-foundries." This shrinks the number of slots in "DFM reference flows," which isn’t good news for niche providers.

I think the primary reasons to be a niche tool provider in the DFM market today are that 1) there is no complete DFM solution yet available – a huge amount of DFM technology still remains to be developed, and 2) particularly in the parametric yield optimization space, new DFM tools – such as those that reduce leakage and variability – provide attractive ROI and may one day expand the horizons of the traditional EDA business. And there's yet another reason – 3) to become a provider of broad, holistic DFM solutions, you probably have to start out as a niche tool provider.

Finally, to go out on a limb a bit – I believe that the pendulum is going to swing back. Within a few years, IDMs and foundries will have concluded that differentiation can no longer come from process technology, and must come from design technology instead – can you say "internal CAD?"

Should this come to pass, it may not be so bad to be a niche DFM tool provider. Recall your own comment about "it’s not a question of if, but when" regarding TSMC one day buying Cadence.

Kahng – In your column about the TSMC Technology Forum, you opined, "the foundries answer to no man …. DFM’s about lock-in. And the foundries have the key." I actually agree with you. In the long term, you’ve got to be right.

The interesting part comes when we look at where we are today.

1) There are quite a few people, for instance, at Qualcomm, Broadcom, nVidia, ATI, Cisco, and so on, whose business strategies depend on having foundries answer to them, and answer smartly at that.

2) The foundries are trying to differentiate while using the same equipment as their competitors, and without providing any unique design tools.

3) And the foundries have never owned or even accessed the chip-level or system-level design content.

So, the question is – how do we get from here to there?

Again, I think the answer is obvious – differentiation by ownership of design technology, and by achieving the best possible combination between foundry process know-how, and foundry-specific design and DFM technologies.