[Editor’s Note: An edited version of this article first appeared on-line in EDA Weekly in January 2004.]

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There’s magic in semiconductor physics and the high priests of that magic are a pretty interesting bunch of guys. Their magic is based on the fact that semiconductors live in limbo – neither are they fully conductors, nor are they fully insulators. The high priests have known for a long time that they can alter the characteristics of a semiconductor by introducing impurities into its molecular structure. The type and quantity of impurity that the high priests introduce into a semiconductor – a process called "doping" – is one of the founding principles of their magic, one that involves all kinds of closely guarded rituals, secret sauces, and soothsaying. But we’ll talk more about the magic in a minute.

Meanwhile, go to your bookshelf and pull down your textbook on electronic devices. Remember that semiconductors basically come in two flavors, p-type and n-type. (That’s "p" for "positive" and "n" for "negative.") In p-type semiconductors, the majority carriers are non-negative charges referred to as "holes." In n-type semiconductors, the majority carriers are negative charges.

Then, remember that a transistor is a device created by sandwiching various semiconductor materials together. Transistors can be pnp or npn depending on how the semiconductor materials are layered. Remember that transistor device behavior is dependent on both the type of semiconductor material and the type/amount of doping inside of that material. Remember also that transistor behavior can be tweaked and twiddled by applying various voltages across the different terminals on the device and/or by subjecting the device to a range of environmental conditions.

Now remember that the BJT (bipolar junction transistor, invented around 1947 at Bell Labs) is a current-controlled device that consists of a thin base region (only lightly doped) sandwiched between the larger emitter and collector regions (both more heavily doped). In the case of the pnp BJT (p-type emitter region, n-type base region, p-type collector region), a voltage is applied across the emitter-base junction, causing majority carriers to flow from the emitter region into the base region – "holes" flow from p-type emitter region into the n-type "hole-depleted" base region.

Meanwhile, a "reverse-bias" voltage applied across the base-collector junction causes "minority" carriers to flow from the base region into the collector region – positive charges flow from the n-type base region to the p-type collector region. Don’t forget, though, that you’ve also got some small amount of current that can also be bled off of the base. (Of course, if you’ve got an npn-type device on your hands, the vice versa of all of this applies.)

The end result is that the emitter current is the sum of the current flowing out of the collector (lots) plus the current flowing out of the base (little), and the BJT is a current-controlled device. The large amount of current coming out of the collector (in the range of mAmps) is "controlled" by the small amounts of current coming out of the base (in the range of microAmps).

Okay, now turn to a different chapter in your textbook. Remember that there’s another class of transistors, the FETs or Field Effect Transistors, and that those bad boys come in two flavors – the metal-oxide semiconductor FET (MOSFET) or the junction field-effect transistor (JFET). They were invented by Shockley in 1955, although if your textbook is worth what you originally paid for it, you’ll see that the history of the FET is actually quite complicated. (Even today it’s somewhat controversial and you should go read the December 1997 issue of the IEEE Journal of Solid-State Circuits, vol. 32, No.12. You should also check out www.bellsystemmemorial/com/belllabs.transistor1.htm.)

Meanwhile, your textbook should be reminding you that you used to know, way back when, that FETs differ from BJTs in that they’re voltage-controlled devices and have only one kind of charge carrier moving around in there. Hence, they’re "unipolar" devices – none of this majority carrier/minority carrier nonsense that’s happening over in the BJT chapter.

Even better, FETs have sources, drains, and gates, which is far more intuitive than that BJT emitter-collector-base deal. And, the other really cool thing about JFETs in particular – they’re channeling Jenny Craig in such a way that one minute they’ve got the anorexic wasp-waste thing going one and the next minute it’s, "Oh my, better move the old belt buckle out a notch or two." Which is just really cool.

Okay, okay, fine. Enough with the textbook. It’s time to get back to the high priests of semiconductor magic. Two of the best and brightest among them are currently working side-by-side at the Agilent Technologies’ Worldwide Process and Technology Center in Santa Rosa, CA.

Dr. David Root is the more senior of the two; Dr. Masaya Iwamoto is the newer member of the team. They spend their days working spells and incantations over small cauldrons full of a variety of toxic ingredients, trying to coax ever more magical and mysterious BJT behaviors out of the lumps that they pull up out of their brew. Oh, and not just timeworn, age-old silicon-based brews for these guys.

Root and Iwamoto are busy with the newer, trendier broths – stuff like gallium arsenide (GaAs) and indium phosphide (InP), stuff that makes their fellow high priests go all a-tingle with the dark, bubbly mystery of what can be done (particularly in those truly spooky wireless devices) when clever mixes and matches are made here.

(Well, okay, okay. In truth, Root and Iwamoto aren’t really manufacturing semiconductors, or BJTs for that matter. What they’re really doing all day is making models of what the lumps and glumps and BJTs would be like if somebody actually were to manufacture them along the lines of the spells and incantations that Root and Iwamoto design. Or in their words: "We feed back our understanding based on modeling, analysis, and characterizations, to those actually designing and fabricating the transistors." An important distinction, no doubt, but you get the idea.)

Anyway, it’s important to note at this point that Root has had his GaAs high priest credentials in place for quite some time, and not just in BJTs, mind you, but in FETs as well. The Root Model (as in "David Root," not as in "root" of the problem) was first announced in a 1991 paper, "Technology Independent Non Quasi-Static FET Models by Direct Construction from Automatically Characterized Device Data" (with Fan and Meyer) in the 21^st European Microwave Conference Proceedings. The article defines a measurement-based FET model for large-signal (nonlinear) simulations of GaAs FETs in both the time and frequency domain. Even today, other high priests are still referencing those seminal incantations.

(For those looking for a more "accessible" version of those particular incantations, Root’s article, "A Measurement-Based FET Model Improves CAE Accuracy," was published in Microwave Journal at the same time.)

Iwamoto, meanwhile, has more recently proven his merit to his fellow high priests in several publications. His papers, "Linearity Characteristics of InGaP/GaAs HBTs and the Influence of Collector Design" (with Asbeck, Low, Hutchinson, Scott, Cognata, Qin, Camnitz, and D’Avanzo in Transactions on Microwave theory and Techniques) and "Large-signal HBT Model with Improved Collector Transit Time Formulations for GaAs and InP Technologies" (with Root, Scott, Cognata, Asbeck, Hughes, and D’Avanzo in 2003 IEEE MTT-S International Microwave Symposium Digest), were both published right here in the new millenium, and were of a caliber that, in conjunction with his Ph.D. thesis (researched and certified by the ECE Department at U.C. San Diego) and numerous summer internships with Agilent, earned Iwamoto the right to become an official high priest working alongside the established and esteemed Root in the Santa Rosa labs. (A run-on sentence, if ever there was one.)

Recently, I was lucky enough to be able to talk to the high priests Root and Iwamoto. And I knew as soon as the conversation started, that they guys are smart. Boy, are they smart! How do I know? Well, you can tell a lot by listening to the nuance in voices when you talk on the phone. The smart ones? They’re really authentic in the way they describe things – especially high priests – and they’re really, really modest. They’ll talk about their own work, but they’ll also tell about the great stuff that others have done, the models and incantations that other high priests have developed for coaxing cool stuff out of the cauldrons and bubbling goo.

Root told me lots about the great stuff that Iwamoto has done. Iwamoto and Root, together, told me about the great stuff that Peter Asbeck and Lovell "Stretch" Camnitz have done (fellow GaAs high priests, one of whom is 6’ 8"). It remained for Joe Civello (ADS Platform Manager for Agilent EEsof EDA) and Lisa Hebert (PR Manager for Agilent) to tell me about Root’s important accomplishments.

Meanwhile, all of them talked about the new Agilent simulation model for high-frequency GaAs and InP heterojunction bioplor transistors (III-V HBTs). (Better go journal hunting again, because this new model was just announced as an Agilent product in the December 2003 issue of Microwave Journal, "A Nonlinear Circuit Simulation Model for GaAs and InP Heterojunction Bipolar Transistors.")

I don’t know about you, but I’m exhausted – all of this and we still haven’t even gotten to the actual interview, the part where Root and Iwamoto tell us in their own words what all they’ve been doing lately in the in Santa Rosa labs. So here it is, at last. The high priests speak …

David: There’s a technical subset of bipolar junction transistors called III-V heterojunction bipolar transistors (III-V HBTs). The III-V means they’re transistors made from semiconductor compounds involving atoms from group III and group V of the periodic table. Examples include bipolar transistors made up of GaAs and InP [as opposed to doped-up ‘pure’ silicon transistors, or SiGe (a IV-IV HBT), which always get a lot of press]. Heterojunction refers to the fact that the transistors are made from junctions of different materials, such as InGaP/GaAs and InGaAs/InP. These extra degrees of freedom (band-gap engineering) enable the design of state-of-the-art high-performance transistors.

The market for GaAs and InP HBTs is not the same as the market for Si-based BJTs. GaAs and InP HBTs are important today because of specific advancements being made for specific applications, such as power amplifiers for handset phones and wireless LANs (GaAs HBTs), and high data rate communication applications (InP HBTs). One of the important issues is how to design products for these markets using these different devices – III-V HBTs versus more common homojunction BJTs. A necessary tool for designs in these technologies is a nonlinear circuit simulation model for III-V HBT devices – which is what Masaya and I have been working on. We’ve developed a new comprehensive nonlinear III-V HBT model, which was announced last December.

Masaya: This model is specifically formulated for III-V HBTs, namely for GaAs and InP HBTs. There has been a lot of previous work on this, but one of the key contributions of this model is the comprehensive nonlinear transit time model, important at high frequencies, that has been shown to be related to distortion. We’re able to get a better prediction of linearity with this nonlinear transistor model.

David: This model is the first to integrate the specific physics of the III-V HBT in a mathematically consistent way and the first to be incorporated in robust production code for a wide variety of heterojunction devices.

Masaya: I started working on this technology when I went to graduate school. I wanted to study HBTs, which is why I went to UCSD. I was aware at the time that Agilent was doing work with GaAs. So basically, during the summers at UCSD, I interned in Santa Rosa. My principal work was in HBT modeling and characterization and that was the work that led to this HBT model. After I finished, I was hired full time and have been here in Santa Rosa for just over a year now. I’m working with David on the III-V HBT model and also involved with HBT process development.

David: Masaya and I have developed this model at the Agilent Worldwide Process and Technology Center, and now we’re working with the EEsof EDA Division to implement a robust version that can be integrated with their design tools.

Joe: The labs and the EEsof Division are adjacent to each other here in Santa Rosa.

David: In the process of working with EEsof, we’ve had the opportunity to work with design houses and foundries to extract our models. In particular, we worked with WJ Communications [the commercial products descendent of Watkins-Johnson] over a year ago to validate the early work. Based on such validations, and those conducted on our own internal Agilent devices, we now have a very accurate robust general model for the III-V HBT device that provides a significant advantage for those circuit designers who are working in high-speed analog circuit design.

Part of our motivation for this work is that III-V HBT devices have different characteristics than silicon BJT devices. The velocity of the charge carriers in III-V HBTs, as a function of the electric field, has a different shape compared to that found in Si BJT devices. That microscopic physical property directly translates into different device level characteristics – the speed of the device, as a function of the applied voltage, for example, has a different shape, which affects how the devices perform in circuits in several ways. So to design in these new III-V heterojunction bipolar processes that behave differently than more traditional processes, it’s important to have accurate nonlinear models of the behavior.

In our labs in Santa Rosa, our colleagues have developed semiconductor processes in these compound materials using a wide variety of techniques. We do FETs (MESFETs and pHEMTs) in GaAs, and now III-V HBTs in GaAs and InP. We’re also developing high-speed broadband ICs from these technologies at our facility. They have been for our internal proprietary use within Agilent for the Test and Measurement Business.

Masaya and I work "between" the semiconductor fabrication engineers and the circuit designers. It’s our job to help characterize, analyze, and model the behavior of the devices we produce for the products we design, as well as feed back information to improve the semiconductor design process. This direct experience with novel in-house semiconductor processes and cutting edge circuit designs is directly responsible for the successful modeling efforts.

Now, we’re working with the EEsof Division to provide this model to our customers. The collaboration is an interdisciplinary one – device physicists, material scientists, characterization engineers, circuit designers, and the first-rate tool design engineers from EEsof, make up our team now providing these tools to external customers.

As we’ve had these models underway internally for a long time, we’re technical pioneers ourselves on behalf of internal users. But to get our models adopted for use by our larger user community, we’ve needed to make an additional effort. Masaya and I have published many of the details of the equations and the formulations. This is necessary to have the model principles of operation understood, a prerequisite for adoption by the wider community. However much of the key IP in the model is in the implementation details – the implementation is proprietary.

Meanwhile, if we can convince people of the material and physical robustness of the work with data from independent non-linear experiments, we will have better success in incorporating our models into the mainstream tools. That will provide benefit to Agilent customers, as EEsof is able to commercialize the models.

Joe: One of the issues around commercialization is for a business division to be convinced by R&D that there’s a market for what’s been developed. From our perspective, before a big market is necessarily recognized, we can observe collaborations that result from work to meet internal needs. The subsequent efforts to develop and prototype models for commercialization is a process that depends on who the players are and where the technology is going. Our implementation engineers work closely with the R&D team through a carefully planned project to do this, but the real research and prototyping phase has already been done for internal users.

David: Part of the effort is getting a commitment from other business divisions to commercialize our work and then to start working together to define the project and have Marketing ratify it. Then, of course, it’s the process of getting the resources to take an internal project and make it into an external project. In the case of the new HBT model, while this process was going on, we were still developing the prototype. We did some customer pre-qualifications of the model based on the perception that we needed to see a real customer at their own foundry to test the model.

Over a year ago, we were able to work with an external foundry and have Masaya extract the new model with respect to their model. We were able to provide an early prototype of our model, which was the feedback that EEsof needed to convince them that the model worked and that there could be an application for a wide variety of customers. We had already done extensive validation of the model with respect to our internally developed devices. It was somewhat annoying that we had another hurdle to jump before commercialization was approved. However, things are certainly moving in the right direction now. Besides, we almost always learn new things from talking with other customers about their needs and problems.

The way we work across the team is fairly straightforward. Masaya will do models and then take those calculations to the group, providing prototypes in electrical form and explicitly listing equations. We have WebEx meetings with key EEsof development engineer Yo-Chien Yuan and other expert coders, and we discuss the implementation with them in detail. They tell us their requirements with regards to customer expectations and, of course, all along we’re working with the EEsof project manager, Steve Chen, to meet a rigorous schedule. There are weekly technical meetings where we get down and dirty into the code.

It’s actually been wonderful to see the synergy between our research and something commercial emerging from our work – something that’s not only useful internally, but that has value when made public. As we’re working with EEsof, we go out to visit customers and see a variety of problems. We see their facilities and their problems and we’re able to deliver solutions.

Masaya: I echo everything that David has said. I don’t have too much experience yet, but in this past year we’ve been meeting with customers and hearing about their issues and problems. It’s been a great experience for me.

Joe: I’ve been with EEsof for 7 years, and the customer excitement I’m seeing with this Agilent HBT is really something. I’m not surprised that David and Masaya see that excitement as they’re working with our customers.

David: It’s been interesting to see the feedback from the customers. They’ve been very impressed that the physics is correct in the models and the ability of the models to accurately predict distortion. Importantly, these models are based on Masaya’s work as a student – the link between distortion and the speed versus bias characteristics of the device. The customers are very appreciative of how well the models are behaving.

Masaya: I recently was able to visit customers in Japan to promote the model. They’re exploring lots of uses for HBTs over there, including power amplifiers. Linearity is important in their applications, and I was encouraged by the positive feedback regarding the technical aspects of this model. They see value in the convergence aspects of our model as well – that the models simulate properly is a key issue with them.

David: The customers have been trying to use silicon-based bipolar models, but these are III-V HBT devices. The physical characteristics of Si BJTs and III-V HBTs are different. For instance, over much of the useful operating range, the speed of a III-V HBT decreases with increased collector voltage. In old-fashioned BJT devices, the speed increases with collector voltage. So it’s the exact opposite. Most customers, if they try to fudge the parameters in those silicon models to fit an III-V HBT device, find difficulties and all kinds of hidden consequences. This leads to restricted and risky applications that are ultimately not the way to go about doing things. You need a real model of the actual device that you’re using, a true III-V HBT model as opposed to a silicon BJT one.

In fairness, there’s been good university work done in this area. The foundation of our work here in Santa Rosa was technical work done at UCSD. We’ve been working with Professor Asbeck at UCSD and Stretch Camnitz at HP, another key contributor, since their seminal paper was first published in 1996 incorporating the basic physics of these devices. There was a consortium between UCSD and HP back in the mid-90’s – before we were Agilent – that also included Rockwell, TRW, Texas Instruments, Cadence, Silvaco, Meta-Software, the University of Illinois, and DARPA. That consortium was driving all of the work that resulted in the DARPA/UCSD model. The model implementation was a prototype with correct physics, but it wasn’t a very commercially robust bit of code that could actually be used by a vast number of people doing design.

Since we had a close collaboration with Stretch, we started from the 1996 work and did some significant additional development to properly describe the operational physics of the non-linear transit time. We cleaned up some of the implementation details of the DARPA/UCSD model, extended it to InP devices – originally it was just for GaAs – and then EEsof robustly implemented it as commercial grade code. The consequences are that the model is more accurate, functions over a wider range of operating parameters, is more robust for convergence, and is faster than the DARPA/UCSD model. We definitely owe a debt of gratitude to Stretch and to Professor Asbeck, whose work went into the Agilent model.

Masaya: I have some brief comments. Peter Asbeck is a world-renowned expert on HBTs. I feel grateful that he was my advisor at UCSD. Basically, the majority of the work was done in the early to mid 1990s. Since then, there haven’t been too many updates to the UCSD model. Presently, Asbeck is still doing research and mulling key issues, but the current efforts is not as a big as what led to the DARPA/UCSD model.

David: My Ph.D. was in abstract theoretical physics. It was abstruse work with no applications. When I came here to what was then HP, I thought I would be doing research on electromagnetism, but they changed their minds after I arrived. I was assigned to work on nonlinear models of transistors, even though I had never taken a single engineering course (except for one semester of linear systems – essentially applied mathematics) during my education. I didn’t know what a transistor was! I only had a math degree and two physics degrees. It took a while for me to bring myself up to speed, but I think my background also freed me from the way in which other people had approached these problems in the past. I was lucky to be able to revisit the problems of nonlinear FETs and to examine the basic architecture of these HBT models.

It’s been a long process for me, but I think my background in theoretical physics was beneficial. Now I feel I’m doing something useful. There’s plenty of room for abstract physics and math in my work, but I’m also helping to solve problems that many people, young students, implementers, and engineers are working on and are interested in. The work is very diverse and interdisciplinary and exciting. I continue to learn each day from the many outstanding colleagues with whom I work. I have to say it’s just been a wonderful experience here since the very beginning.

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Editor’s note: According to Agilent: " Dr. David Root, Principal Scientist & Acting Tools Manager, Worldwide Process & Technology Centers, is an Agilent guru on high frequency modeling. He works in the company's Microwave Technology Center and has done research on device and behavioral models for years." I ask you, what’s the difference – "guru" versus "high priest."

Meanwhile, it’s actually quite frustrating at times to engage high priests in conversation. Whole hosts of questions come to you only later, days after the encounter has taken place. But by that time, they’ve gone back into their labs and the doors have been sealed shut once again. Nonetheless, my thanks to Caroline Melnicoff who worked her own special brand of magic to make this article happen.

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May 11, 2005

Peggy Aycinena owns and operates EDA Confidential. She can be reached at peggy@aycinena.com

Copyright (c) 2005, Peggy Aycinena. All rights reserved.